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Application of a floating well concept to a latch-up-free, low-cost, smart power high-side switch technology
Bafleur, Marise; Buxo, Juan; Puig i Vidal, Manuel; Givelin, P.; Macary, V.; Sarrabayrouse, G.
Universitat de Barcelona
The aim of this brief is to present an original design methodology that permits implementing latch-up-free smart power circuits on a very simple, cost-effective technology. The basic concept used for this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up.
2010-05-04
Circuits integrats
Circuits electrònics
MOS integrated circuits
Power integrated circuits
Switching circuits
(c) IEEE, 1993
Article
IEEE
         

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