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Implementing end-to-end register data-flow continuous self-test
Carretero Casado, Javier Sebastián; Chaparro, Pedro; Vera Rivera, Francisco Javier; Abella Ferrer, Jaume; González Colás, Antonio María
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
While Moore's Law predicts the ability of semiconductor industry to engineer smaller and more efficient transistors and circuits, there are serious issues not contemplated in that law. One concern is the verification effort of modern computing systems, which has grown to dominate the cost of system design. On the other hand, technology scaling leads to burn-in phase out. As a result, in-the-field error rate may increase due to both actual errors and latent defects. Whereas data can be protected with arithmetic codes, there is a lack of cost-effective mechanisms for control logic. This paper presents a light-weight microarchitectural mechanism that ensures that data consumed through registers are correct. The structures protected include the issue queue logic and the data associated (i.e., tags and control signals), input multiplexors, rename data, replay logic, register free-list and release logic, and register file logic. Our results show a coverage around 90 percent for the targeted structures with a cost in power and area of about four percent, and without impact in performance.
2012-07-18
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
Data flow computing
Program verification
Flux de dades
Microarquitectura
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