The memory hierarchy is one of the most important elements in the performance of nowadays processors. In order to reduce the latency of memory accesses, there are a lot of different ways to improve the memory hierarchy. One way is making use of prefetching mechanisms. These mechanisms try to predict which data the processor is going to need and take it to the nearest cache level before it is demanded by the application. This Master thesis consists in two main parts; the first one is comparing and analyzing the most recent prefetching techniques with the same simulation infrastructure. This analysis will allow us to know which are the advantages and disadvantages of each mechanism in different hardware configurations. The second main part consists in building an independent module for the prefetcher in order to be exported to any other simulation platforms.