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Design of complex circuits using the via-configurable transistor array regular layout fabric
Pons Solé, Marc; Moll Echeto, Francisco de Borja; Rubio Sola, Jose Antonio; Abella Ferrer, Jaume; Vera Rivera, Francisco Javier; González Colás, Antonio María
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors; Universitat Politècnica de Catalunya. Departament d'Enginyeria Electrònica
Layout regularity will be mandatory for future CMOS technologies to mitigate manufacturability issues. However, existing CAD tools do not meet the needs imposed by regularity constraints. In this paper we present a new method for regular layout generation with Via-Configurable Transistor Arrays focusing on reducing the area overhead associated to regularity. Results for ISCAS85 benchmarks in the 45nm technology node are provided showing that comparable areas to the standard cell approach can be obtained.
2012-05-10
Àrees temàtiques de la UPC::Enginyeria electrònica i telecomunicacions::Microelectrònica::Circuits integrats
Integrated circuits.
Circuits integrats
Circuits integrats digitals
Restricted access - publisher's policy
Conference Object
IEEE Computer Society Publications
         

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