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Hardware/software-based diagnosis of load-store queues using expandable activity logs
Carretero Casado, Javier Sebastián; Vera Rivera, Francisco Javier; Abella Ferrer, Jaume; Ramírez García, Tanausu; Monchiero, Matteo; González Colás, Antonio María
Universitat Politècnica de Catalunya. Departament d'Arquitectura de Computadors
The increasing device count and design complexity are posing significant challenges to post-silicon validation. Bug diagnosis is the most difficult step during post-silicon validation. Limited reproducibility and low testing speeds are common limitations in current testing techniques. Moreover, low observability defies full-speed testing approaches. Modern solutions like on-chip trace buffers alleviate these issues, but are unable to store long activity traces. As a consequence, the cost of post-Si validation now represents a large fraction of the total design cost. This work describes a hybrid post-Si approach to validate a modern load-store queue. We use an effective error detection mechanism and an expandable logging mechanism to observe the microarchitectural activity for long periods of time, at processor full-speed. Validation is performed by analyzing the log activity by means of a diagnosis algorithm. Correct memory ordering is checked to root the cause of errors.
2012-05-10
Àrees temàtiques de la UPC::Informàtica::Arquitectura de computadors
Fault detection and isolation (Control enigeering)
Program verification
Computer architecture
Programari -- Control de qualitat
Arquitectura d'ordinadors
Restricted access - publisher's policy
Conference Object
IEEE Press. Institute of Electrical and Electronics Engineers
         

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